1. Field of the Invention
This disclosure relates to an electrical testing method for a semiconductor package, and more particularly, to an electrical testing method for a semiconductor package related to socket defects on a device under test (DUT) board.
2. Description of the Related Art
A tester is an automated device combining hardware and software for performing an electrical test of a semiconductor device. Generally, memory semiconductor devices such as dynamic random access memories (DRAMs) gradually increase in capacity and the number of pins. Accordingly, a tester for the semiconductor memory device has been developed that focuses on high throughput.
When the capacity of the semiconductor memory device becomes larger, the cost for the electrical test increases since the time required to perform the electrical test increases. Thus, in order to solve the above problem, the tester for the semiconductor memory device generally adopts a parallel testing method.
The parallel testing method is a method for testing a plurality of semiconductor devices at one time, instead of testing the semiconductor devices one by one. The parallel test for 32 and 64-DRAM devices has been utilized, and the parallel test for 128-DRAM semiconductor device is about to be utilized.
FIG. 1 is a block diagram for illustrating conventional concepts of the tester for testing a device under test (DUT). Referring to FIG. 1, the tester 1000 comprises a micro processor 1100 therein for controlling entire tester, and the micro processor 1100 is operated with a file memory 1200 to store program files required to test the semiconductor device electrically, store the testing results, and store system programs required to control entire tester 1000.
In addition, in the tester, hardware required to test electrically the semiconductor device such as a timing generator, a pattern generator, a wave formatter, a logic comparator, a power source for input/output, a direct current (DC) measuring unit, and a programmable power supply are built-in. The tester 1000 is generally operated with an automated robot known as the handler (2000 in FIG. 2). Thus, the DUT is loaded on a test site 2100 existing in the handler, and the functions are tested electrically.
FIG. 2 is a block diagram for describing functions of the conventional handler. Referring to FIG. 2, the handler 2000 is an automated testing robot independently controlled by a micro processor 2200 that communicates with the micro processor in the tester 1000. The handler 2000 includes a loading unit 2300 for loading the DUT from the outside and moving the DUT to the test site 2100 therein. Also, the handler 2000 includes an unloading unit 2400 for conveying the tested DUT to the outside. The handler 2000 also includes a discriminating unit 2500 that receives the electrical test results from the tester 1000 through an information signal cable 2700 to discriminate whether the DUT is acceptable or not.
A test site temperature controlling unit 2600 controls a temperature of an area where the DUT is tested. For example, the test site 2100 may be at high temperature, a room temperature, or a low temperature, to test whether the semiconductor device performs correctly regardless of the changes in the temperature. The test site 2100 is an area electrically connecting the DUT with the tester 1000 through a DUT board, and is connected to the tester 1000 via a test signal cable 2800.
Thus, the handler 2000 loads the DUT from outside so that it is connected to the tester 1000 via the information signal cable 2700 and the test signal cable 2800, and carries the DUT on a socket of the DUT board existing on the test site 2100, and after that, transmits a test start signal to the tester 1000. When the handler 2000 receives a test ending signal from the tester 1000, it discriminates the DUT on the socket and unloads the DUT according to the test result received with the test ending signal.
FIG. 3 is a plane diagram illustrating the conventional DUT board mounted on the test site of the handler. Referring to FIG. 3, the DUT board 2110 has a configuration that a plurality of sockets 2104 are mounted on a printed circuit board 2102 in a matrix form. However, the socket 2104 does not last permanently, and defects are often generated as the socket 2104 becomes worn and damaged. Accordingly, the tester may perform an abnormal electrical test for the DUT. Thus, the accuracy of the electrical test is reduced because of a quality problem, and re-test should be performed.
To solve the above problem in advance, the socket defects of the DUT board should be quickly found and the defects should be fixed or replaced. However, it is difficult to recognize the states of a plurality of sockets mounted on a lot of DUT boards, and to fix or replace the sockets. Also, since many other defects may be generated during the fixing and replacing of the sockets by manual work, the socket test through automation is considered a more effective solution for solving the above problems.
Embodiments of the invention address these and other disadvantages of the conventional art.